Secure Dual-Hardware Locking System
An air-gapped physical firewall architecture that physically decouples wireless RF communication from lock actuation logic. A Sipeed Tang Nano 20K FPGA acts as an immutable Hardware Root of Trust executing a cycle-accurate 16-bit Galois LFSR (polynomial x^16 + x^14 + x^13 + x^11 + 1) generating 65,535 non-repeating dynamic OTP codes rotated every 60 seconds. Wireless transmission is handled by an ESP32 running router-less ESP-NOW connected to the FPGA via a strictly unidirectional Simplex Optical UART link, guaranteeing 100% immunity to remote buffer overflows and replay attacks.
Core Logic
Gowin GW2AR-18C FPGA (20K LUTs)
RTL Primitive
16-bit Galois LFSR (65,535 cycle OTP)
Physical Isolation
Simplex Optical UART (Air-Gapped)
RF Transport
ESP32 ESP-NOW Unicast Protocol